摘要 :
3-D systems and chiplets pose a significant challenge for reliable timing of heterogeneous integrated systems. Delay locked loops are capable of synchronizing clock signals; however, the increasing speed of deeply scaled technolog...
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3-D systems and chiplets pose a significant challenge for reliable timing of heterogeneous integrated systems. Delay locked loops are capable of synchronizing clock signals; however, the increasing speed of deeply scaled technologies leads to large and complex delay lines. In this paper, a dual sawtooth-based delay locked loop is proposed to address the increasing difficulty of delay generation in high speed 3-D systems. The proposed architecture lacks a traditional voltage controlled delay line in favor of differential integrators to generate the target delay. The architecture is verified using PTM 7 nm models and achieves locking speeds as low as six cycles for a 1 GHz clock signal.
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The rise of mobile technologies and cloud computing has increased the importance of energy consumption. On-package voltage stacking, where current is recycled between multiple cores, is a potentially effective solution to this gro...
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The rise of mobile technologies and cloud computing has increased the importance of energy consumption. On-package voltage stacking, where current is recycled between multiple cores, is a potentially effective solution to this growing issue. Two converters, a load-to-load ladder buck converter and a bus-to-load isolated resonant converter, are particularly appropriate for on-package voltage stacking. A four core system composed of either converter topology is evaluated under several current mismatch scenarios in terms of transient and DC voltage drops, voltage ripple, settling time, and power efficiency. The load-to-load buck converter exhibits higher power efficiency and smaller transient voltage drops as compared to the bus-to-load resonant converter. The resonant converter is lower cost, smaller in area, and provides isolation.
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The stochastic behavior of magnetic tunnel junctions (MTJ) finds use in many applications - from analog-to-digital conversion to neuromorphic computing. In this paper, a dithering method exploiting the stochastic behavior of an MT...
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The stochastic behavior of magnetic tunnel junctions (MTJ) finds use in many applications - from analog-to-digital conversion to neuromorphic computing. In this paper, a dithering method exploiting the stochastic behavior of an MTJ, based on the voltage controlled magnetic anisotropy effect, is proposed. This method is used to measure low frequency analog signals over an interval. The circuit is composed of two MTJ devices that convert an analog signal into a series of high resistance and low resistance stochastic states, creating a dithering effect. The behavior of the input signal is extracted from the switching frequency. The binary nature of the output signal reduces the complexity, enabling a small, fast, and energy efficient circuit for extracting different forms of information from an analog signal.
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The stringent requirements of power noise on complex multi-domain power delivery networks (PDN), and the complicated relationship between signal integrity and power integrity (PI) have led to an ever challenging PI sign-off proces...
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The stringent requirements of power noise on complex multi-domain power delivery networks (PDN), and the complicated relationship between signal integrity and power integrity (PI) have led to an ever challenging PI sign-off process. A lumped PDN model is widely used, where the power network is treated as a two-port network with the impedances extracted by an electromagnetic solver. A distributed model of the power network is however preferred during a PI sign-off flow, providing a more accurate circuit model for time domain simulations. Hundreds or even thousands of ports need to be properly evaluated during the PDN extraction process, which can be computationally expensive and error prone. A Python tool is described here to enable a fast and configurable process for distributed port assignment during the PDN extraction process. An enhanced automation flow, integrated with the Python tool, has also been developed to support early power network exploration. In one case study, a 360X speedup in the port assignment process is achieved while revealing a high risk power network within the package. The proposed automation flow is versatile and highly adaptive for different power network topologies.
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摘要 :
Due to the increasing throughput of high performance integrated circuits, the power consumption of recent high performance computing systems has grown significantly, leading to high on-chip current demand. The large current flowin...
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Due to the increasing throughput of high performance integrated circuits, the power consumption of recent high performance computing systems has grown significantly, leading to high on-chip current demand. The large current flowing within the power delivery network leads to challenging issues such as electromigration, low power efficiency, and thermal hotspots. As a technique to reduce on-chip current demand, voltage stacking has become a topic of growing interest within the industrial and academic communities. The challenges of on-chip voltage stacking are however significant. The limitations of relying on on-chip decoupling capacitors when load imbalances occur within a high current system are reviewed. To manage these load imbalances, a ladder topology switched capacitor converter is proposed to regulate the voltages between layers within a voltage stacked system. A 20X improvement in voltage drop is demonstrated on a case study. The current path within a voltage stacked system is quite different from a standard system. A horizontal current path is formed due to the serial connection between layers, producing large parasitic impedances within the power network. The on-chip power network within a voltage stacked system therefore requires careful consideration and specialized design techniques.
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摘要 :
The stringent requirements of power noise on complex multi-domain power delivery networks (PDN), and the complicated relationship between signal integrity and power integrity (PI) have led to an ever challenging PI sign-off proces...
展开
The stringent requirements of power noise on complex multi-domain power delivery networks (PDN), and the complicated relationship between signal integrity and power integrity (PI) have led to an ever challenging PI sign-off process. A lumped PDN model is widely used, where the power network is treated as a two-port network with the impedances extracted by an electromagnetic solver. A distributed model of the power network is however preferred during a PI sign-off flow, providing a more accurate circuit model for time domain simulations. Hundreds or even thousands of ports need to be properly evaluated during the PDN extraction process, which can be computationally expensive and error prone. A Python tool is described here to enable a fast and configurable process for distributed port assignment during the PDN extraction process. An enhanced automation flow, integrated with the Python tool, has also been developed to support early power network exploration. In one case study, a 360X speedup in the port assignment process is achieved while revealing a high risk power network within the package. The proposed automation flow is versatile and highly adaptive for different power network topologies.
收起
摘要 :
Due to the increasing throughput of high performance integrated circuits, the power consumption of recent high performance computing systems has grown significantly, leading to high on-chip current demand. The large current flowin...
展开
Due to the increasing throughput of high performance integrated circuits, the power consumption of recent high performance computing systems has grown significantly, leading to high on-chip current demand. The large current flowing within the power delivery network leads to challenging issues such as electromigration, low power efficiency, and thermal hotspots. As a technique to reduce on-chip current demand, voltage stacking has become a topic of growing interest within the industrial and academic communities. The challenges of on-chip voltage stacking are however significant. The limitations of relying on on-chip decoupling capacitors when load imbalances occur within a high current system are reviewed. To manage these load imbalances, a ladder topology switched capacitor converter is proposed to regulate the voltages between layers within a voltage stacked system. A 20X improvement in voltage drop is demonstrated on a case study. The current path within a voltage stacked system is quite different from a standard system. A horizontal current path is formed due to the serial connection between layers, producing large parasitic impedances within the power network. The on-chip power network within a voltage stacked system therefore requires careful consideration and specialized design techniques.
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